As semiconductor technology advances into the deep sub-micron process nodes, short channel effects can severely degrade performance. The carrier velocity saturates in such short channels, which slows switching speeds and reduces transistor strength. To achieve high density yet have adequate transistor strength, strain engineering techniques have been developed so that the crystal lattice is strained in the source and drain diffusion regions (these diffusion regions are typically denoted as oxide definition (OD) with regard to transistor layout terminology). The OD is not only doped n-type or p-type as appropriate to achieve the desired transistor type (NMOS or PMOS), but is also strained to increase carrier velocity and transistor strength. In that regard, the OD is just locally strained as opposed to straining the entire substrate.
Such local strain has proven to be superior to a global strain across the entire substrate. The type of strain depends upon the transistor type. The OD for PMOS transistors is compressively strained whereas the OD for NMOS transistors has tensile strain. For example, a film of SiGe may be applied to p-type OD to introduce compressive strain whereas a film of SiN or SiC may be applied to n-type OD to introduce tensile strain. The resulting strain engineering of silicon has proven to be quite successful for the achievement of satisfactory transistor strength in deep sub-micron process nodes.
The use of strain engineering introduces a number of constraints into the layout process. FIG. 1 illustrates the layout for an example pair of transistors. A first transistor 100 has its source (S) and drain (D) defined by a first OD region 105. A polysilicon gate 110 separates the source and drain regions. A similar arrangement of another OD region 115 and polysilicon gate 120 defines another transistor 101. At advanced process nodes, the layout of FIG. 1 would be inefficient because OD 115 and 110 forming the drain and source regions are both relatively short. Such a short length to the OD allows its crystal lattice to relax too much despite the use of local strain engineering. Transistors 100 and 101 would thus be too weak. In contrast, if ODs 105 and 115 could be extended to form a continuous OD as shown by the dotted lines 125, ODs 105 and 115 could have increased strain, resulting in better performance. But such an extension of the ODs would short the drain of transistor 100 to the source of transistor 101.
To achieve satisfactory transistor performance in the deep sub-micron process nodes, “continuous OD” layouts have been developed. FIG. 2 illustrates an example layout for a continuous OD 200. Transistors 100 and 101 are still defined with respect to polysilicon gates 110 and 120, respectively. But OD 200 is continuous for both transistors such that it can develop adequate lattice strain for satisfactory transistor strength. A dummy polysilicon gate 205 electrically isolates transistors 100 and 101 by being configured to be charged to the source voltage. For example, if OD 200 is doped p-type, dummy gate 205 would be tied to the power supply voltage VDD. Alternatively, if OD 200 is doped n-type, dummy gate 205 would be tied to ground. A similar dummy gate 210 isolates transistor 100 from a transistor (not illustrated) to the left of dummy gate 210 in continuous OD 200.
Although the use of continuous OD 200 enables sufficient crystal lattice strain to be achieved, there are a number of design complications. For example, each transistor may be considered to reside within a separate “standard cell.” A standard cell 201 that forms transistor 100 extends from a border A along dummy gate 210 to a border B along dummy gate 205. Each dummy gate is always tied to a source voltage—in a PMOS embodiment, the source voltage is VDD whereas it is ground in an NMOS embodiment. An interconnect 215 provides the source voltage coupling between dummy gate 205 and the source of transistor 101. Similarly, an interconnect 220 provides the source voltage coupling between dummy date 210 and the source of transistor 100. With this standard cell topology in mind, note the problems that arise with regard to characterizing the leakage for standard cell 201. With regard to the leakage from the drain for transistor 100, it can only be defined at the cell level with regard to the leakage across gate 110 from the source for transistor 100. But this leakage current from the source for transistor 100 in turn depends upon the state for diffusion region 225 to the left of dummy gate 210. A priori, before standard cell 201 is instantiated next to another standard cell, it cannot be known whether diffusion region 225 is the source or the drain for another transistor in this additional standard cell. This uncertainty greatly complicates the leakage calculation for transistor 100. For example, suppose diffusion region 225 forms another transistor source—it will then be at the same voltage as the source for transistor 100 such that no leakage can occur across dummy gate 210. Conversely, if diffusion region 225 forms another transistor drain, then a leakage current will flow from the source for transistor 101 to diffusion region 225. We know that a leakage current will always be present across gate 110 between the drain and source for transistor 100. This leakage current may be denoted as the “always-present” leakage current to distinguish it from the “optional” leakage current that depends upon whether diffusion region 225 forms a drain or a source. So there exists two possibilities for a standard cell such as cell 201: just the always-present leakage current or a sum of the always-present leakage current and the optional leakage current. The leakage current characterization is a very important performance hallmark of a design. But the conventional standard cell architecture shown in FIG. 2 for continuous OD 200 greatly complicates the leakage current determination for a given design.
Accordingly, there is a need in the art for improved standard cell continuous OD architectures